The invention relates to a circuit arrangement for echo cancellation including a network of capacitors which take part in digital to analog conversion of digital compensation signals supplied by an adaptive transversal filter, in the subtraction of such compensation signals converted to analog signals from echo-laden wanted signals, and also in the analog to digital conversion--done by the iterative method--of the resultant signals from the compensation process which may be laden with a residual echo signal for provision to the transversal filter as a digital correction signal. The upper plates of the capacitor network, forming one terminal of the network, are connected together, and further, insofar as they are correlated with a bit of a group of the more significant bits of the digital signals to be processed, are binary-stepped in their capacitance and can be switched by their lower plates forming separate terminals of the network selectively to ground potential or to a reference potential, or, insofar as they are correlated to bits of a group of the less significant bits of such digital signals, can be applied by their lower plates selectively to ground potential or to a fraction of this reference voltage potential corresponding to the bit combinations of the correlated less significant bits.
A circuit of this kind is known from E. Agazzi's publication "Large Scale Integration of Hybrid Message Digital Subscriber Loops", a dissertation at the University of California in Berkely California, dated May 20, 1982, and comes quite close to meeting the requirements of an ideal echo canceller. These requirements include that, because of the high scanning rate, which is double the bit rate of the digital signals, within the cycle time of, for example, 3.1 microseconds, as low as possible a number of successive processes should be performed. Further it is required that the digital to analog converter has a monotonic converter characteristic, which moreover shows only slight nonlinearities. The resolution for positive and negative signal amplitudes should be at least 12 bits including the sign bit; for the analog to digital conversion of the residual signal, a resolution of up to 8 bits is required for a short adaptation time of the echo canceller. Balancing processes, which constitute a major cost factor, should be avoided. Lastly it is desirable that such an echo canceller, or respectively the analog section thereof, to which the above-described capacitor network belongs, should be realized with a minimum of chip surface in CMOS technology.
The known circuit arrangement, unlike other known circuit arrangements operating with capacitor networks, is able, as indicated, to subject any residual signal that may remain after a compensation process to an analog to digital conversion in order to obtain a digital correction signal for the transversal filter of the compensation circuit. However, the digital correction signal is developed from an additional capacitor which is not correlated with the most significant bit and serves for storing the signal voltage.
In the known circuit arrangement, a comparator in the form of an operational amplifier is, as indicated, connected to the capacitor network. In order to make the evaluation of the voltage values, to which the capacitors of the network become charged, independent of the offset voltage of the operational amplifier by this comparator, the offset voltage is either stored during the sampling of the input voltage of the capacitor network, that is, of the echo-laden wanted signal voltage on the binary-stepped capacitors of the network, in that the input and output of the operational amplifier are connected to one another, or else the input of the comparator is grounded and thus the offset voltage stored on a capacitor formed from capacitive parameters of the comparator. The circuits used for this are transistor switches. In both methods of taking the offset voltage into consideration, with the closing of the respective switching transistors through the gate to drain capacitance, charge is drawn and thereby the potential at the comparator input is changed, which may lead to faulty comparison results. Also capacitive coupling-in of interference voltages onto the comparator input may lead to interferences.
The object of the invention therefore is to design an echo canceller circuit of the above-mentioned kind so that such disadvantageous effects are excluded.